Digital information technology is based on storing data items and sequences of commands that will process the data items stored inside a digital system in a subunit called `memory`. The memory units belong to different kinds based on the type of technology and the nature of accessing locations within a memory unit. The smallest amount of data that can be stored is a binary digit or a "bit". Data items such as integers, real numbers, ASCII characters are represented in terms of bits. A bit has only two values, 0 and 1. Historically, either magnetic fields or electrical signals can be used to represent these two values. A memory unit has a size representing the number of distinct locations, and each location has an address. The number of bits that constitute the content of a memory word is known as the word length.
A memory unit is classified as a "Random Access Memory" (RAM) or a "Sequential Access Memory" depending on whether accessing a word takes a source time no matter where the word is located or whether a sequential search of all previous locations is involved to reach the desired location, respectively. Semiconductor memory with decoding mechanisms is a RAM, and memory units such as tape drives, bubble memory, charge-coupled devices (CCD) are examples of sequential access memory units.
RAM memories are also called read/write memories (RWM) because we can read a word from a location in RAM and we can also write a word to a location in RAM. In contrast, a ROM is a read-only memory. We cannot perform a write operation routinely in a ROM.
A RAM being a read/write memory, should retain the data stored indefinitely without a power supply. Such a RAM is called a nonvolatile memory. The magnetic core memories of the previous decades are nonvolatile memories, but the read/write access is very slow for these memories. A static RAM (SRAM) is a RAM that retains the data so long as the power supply is not disconnected. Most semi-conductor RAM units fall into this category.
A "Dynamic RAM" (DRAM) is a unit where the unit not only needs a power supply, but also the contents of all memory locations will have to be refreshed at regular intervals of time, for otherwise the electrical signal representing data bits will degenerate and no longer represent the correct data. The main reason why a DRAM is designed is because takes only one transistor (FET) and a capacitor to store a bit unlike a semiconductor memory where a bistable flip-flop consisting of four to six transistors is required to store one bit. In high density CMOS VLSI design, we can save a great deal of money and space by using DRAMS. A price is paid for this savings by requiring that a refreshing pulse continuously sweep the DRAM, refreshing the memory contents at regular intervals of time. Refreshing always involves reading the degenerated data at a location, and writing the source value afresh back at that location. No read or write access of this location is allowed when refreshing a location. Refreshing is necessary due to the decay of charge across a capacitor.
Nowadays DRAM chips are available with capacities in range of 16 to 64 megabits. The word length is usually one or two bits and may be extended to any length theoretically. The number of address lines correspond to the number of locations and to the length of the basic addressable word. For example, 16 megabits with one bit per word in one chip will need 22 address lines to address each location. If we need 16 megaword memory, each word with a length 16, then we can use 16 of these chips and connect them in parallel to increase the word length to 16. Word length has no direct bearing on the addressability of a word. However, chips with longer word lengths will need more data pins, more complicated buffers and other circuitry. At high densities, the manufacturing process also becomes more unreliable, cutting down on the net yield. It is for this reason that the cost associated with wide DRAM is rather high.
Refreshing of the data is seldom done on cell by cell basis. RAM locations are logically organized in a number of rows and usually an equal number of columns. For example, in a 16.times.1 megabit DRAM, there will be 2048 rows and that many columns. The address is broken into two halves, and the row value is given to a row decoder. There is a RAS pulse to access a row (for `row address strobe`), and a CAS pulse to access a column (for `column address strobe`). When a row is selected, the complete row is refreshed at one time. This requires only 2048 refreshing, rather than 16 mega refreshings.
The two most important operations on a DRAM are reading and writing. For the both operations, the address of the location is placed in the address register. For reading, "read enable" (RE) is activated and the contents of the entire row are latched into a row latch. The column bits of the address register are then used to identify the column. The bit value at the selected column will be placed onto the output data line. This value is also written back at the source location as `read` is always destructive. For write operation, output data line is disabled, input data line is enabled, "write enable" (WE) is asserted and then CAS is asserted. The value at the input data line will be written at the correct location.
Different manufacturers use different techniques to refresh the memory. In some chips, an internal counter is used to count the row being currently refreshed. Counter value is incremented after each refreshing and the process continues. In some other chips, the address of the row to be refreshed is supplied externally. There is no need to follow any definite order to refresh the rows, so long as each row is refreshed before the change across the capacitor drops below the minimum value representing a "1" value.
For the construction of highly integrated memory chips, the concept of DRAM is now generally accepted. Today's DRAM chips have the capacity of up to 64 megabit. With the continuing development of larger and larger memory chips, various forms of organization have been established. Some of them aim at reducing the access time and avoiding delay caused by periodical refreshing the information stored in dynamic memory. For these reasons, specifically but not exclusively, DRAM is divided into several banks. In the course of operation, each bank has to be accessible and therefore a decoding logic circuitry of a memory controller has to be provided.
In a prior art bank decoding means of DRAM controller system, a complex complementary logic is used for the decoding of each memory bank constituting a DRAM. The approximate volume of the decoding logic for bank.sub.M+1, for example, is equal to the number of DRAM types supported in bank.sub.M+1 multiplied by the decoding logic for bank.sub.M. By DRAM types, it is meant that the decoding logic for bank.sub.M+1 must consider all the possible conditions in bank.sub.0 to bank.sub.M, i.e. the last bank is the most complicated one. So if the system supports a DRAM consisting of several banks having different memory capacities, a substantially intricate logic is necessary to address the required bank in the DRAM.
FIG. 1 of the accompanying drawings exemplifies the above situation with decoding logic circuits for identifying the necessary DRAM bank. In this example, a DRAM controller supports one configuration of 4 MB in bank.sub.0, 1 MB in bank.sub.1 and 8 MB in bank.sub.2, and another configuration of 2 MB in bank.sub.0, 1 MB in bank.sub.1 and 2 MB in bank.sub.2. Decoding logic for bank.sub.2 for the conditions mentioned is shown in FIG. 1 where more logic circuits are implied for further bank configurations.
FIG. 1 shows the conventional method of decoding in which the decoding process of bank.sub.2 must consider all possible combinations of bank.sub.0, bank.sub.1 and bank.sub.2. In a conventional DRAM controller, only two to four banks can be controlled. In a modern DRAM controller, more than eight DRAM banks must be controlled. It is therefore very difficult to implement a conventional decoding method in such a modern DRAM controller.
In FIG. 1, A[n:20] stand for the address bits in terms of MBs. That is, the first 20 bits of the address will define one megablock of memory. Therefore, A[n:20]=0 . . . 000101 stands for the fifth megablock.
Consider the upper branch of FIG. 1. If bank.sub.0 has a size of 4 MB, addressed physically by 0, 1, 2, and 3; and bank.sub.1, has a size of one MB addressed physically by a value 4, then the bank.sub.2 of a size of 8 MB will have addresses 5, 6, 7, 8, 9, 10, 11, and 12. The first AND gate will take care of block address 5. The second AND gate takes care of the two blocks with addresses 6 and 7. The third AND gate will take the next four blocks, 8, 9, 10, and 11. Finally, the last AND gate will address the block number 12.
Consider now the lower branch of FIG. 1. If bank.sub.0 is 2 MB covering the addresses 0 and 1 and bank.sub.1 is 1 MB covering address 2, then bank.sub.2 with 2 MB size is addressed by the two addresses 3 and 4. This is shown in the last AND gates.
The output of FIG. 1 will be the address of bank.sub.2.
Therefore, a need exists for a simpler and cheaper bank decoding circuitry which could easily satisfy different DRAM modules configurations and provide better bank decoding timing.
It is therefore an object of the present invention to simplify the bank decoding logic and to reduce its cost.
It is another object of the present invention to provide better decoding timing.
It is a further object of the present invention to provide means easy to support any kind of configuration of DRAM modules.